| 摘要 |
Integrated circuit inductance structure comprises: silicon substrate (2); planar winding(s) of a conductive track (1); resistive layer (11), unetched and under the winding; dielectric layer (3) between the winding and the resistive layer; and discontinuous conductive sections (12) individually parallel to a portion of the winding which is the closest and electrically connected to ground and to the resistive layer. <??>Preferred Features: The discontinuous conductive sections (12) are out of true with the winding. Each conductive track (1) is located as near as possible to the nearest portion of the winding. Each portion of the winding is connected to several conductive sections (12). <??>The conductive sections (12) are produced in the same metallic level as the conductive track (1) forming the inductance. <??>The resistive layer has a level of doping of 10<16> to 10<19> atoms/cm<3>, preferably 10<17> atoms/cm<3>. <??>The conductive sections (12) are connected to a contact point by several conductive tracks. Each conductive track is positioned such that the resultant of the electromotive forces induced by the inductance is substantially zero. |
