| 摘要 |
A memory architecture for a video graphics controller includes a dynamic random access memory (DRAM), a static random access memory (SRAM) and a bus. The DRAM includes a data port, an address decoder that can receive an address to select a memory location in the DRAM and a command instruction bus that can receive instructions for data transfer. The SRAM includes a first data port to transfer data with the DRAM, a second data port to transfer data with other than the DRAM, a first address decoder that can receive an address to select a memory location in the SRAM for data transfer with the DRAM, a first read/write input that can receive a signal for data transfer with the DRAM, a second address decoder that can receive an address to select a memory location in a page of the SRAM to transfer data with other than the DRAM and a second read/write input that can receive a signal for data transfer from other than the DRAM. The bus is coupled between the data port of the DRAM and the first data port of the SRAM for data transfer between the DRAM and the SRAM.
|
