| 摘要 |
Semiconductor circuit design methods, semiconductor processing methods, and related integrated circuitry are described. In one embodiment, a spacing constraint is defined and describes a desired spacing between a transistor gate line and a next adjacent structure. A circuit layout is defined to include a plurality of transistor gate lines. From the circuit layout, at least one area is determined wherein the spacing constraint is not met. The circuit layout is modified by defining in the one determined area, at least one added space-compensating structure which is laterally spaced from a gate line and a next adjacent structure where the spacing constraint is not met. In another embodiment, a plurality of gate lines are defined which are to be formed over substrate active areas. A determination is made whether a gate line spacing constraint is met wherein the gate line spacing constraint describes a desired spacing between a transistor gate line and a next adjacent transistor gate line. If the spacing constraint is not met, then a space-compensating transistor gate line is added and positioned to satisfy the spacing constraint.
|
