| 摘要 |
For fabricating a field effect transistor on a semiconductor substrate, a gate dielectric of the field effect transistor is formed on a semiconductor substrate. A doped gate electrode, which may be comprised of silicon germanium (SiGe) for example, is formed on the gate dielectric. An amorphous semiconductor structure, which may be comprised of amorphous silicon for example, is formed on the doped gate electrode. A hardmask structure comprised of a hardmask dielectric material is formed on the amorphous semiconductor structure. The gate dielectric, the doped gate electrode, the amorphous semiconductor structure, and the hardmask structure form a gate stack. Liner dielectric structures are formed on sidewalls of the gate stack. A dopant is implanted into exposed regions of the semiconductor substrate after forming the liner dielectric structures on the sidewalls of the gate stack. For example, halo dopant may be implanted at an angle toward the sidewalls of the gate stack for forming halo regions of the field effect transistor. In this manner, the liner dielectric structures on the sidewalls of the gate stack prevent bombardment of implantation ions against the sidewalls of the doped gate electrode to prevent contamination of the implantation chamber. In addition, the amorphous semiconductor structure on top of the doped gate electrode prevents out-diffusion of the germanium from the doped gate electrode since germanium substantially does not diffuse through amorphous silicon. The hardmask structure on the amorphous silicon structure prevents bombardment of implantation ions against the top of a semiconductor material of the gate stack to further prevent contamination of the implantation chamber.
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