| 摘要 |
A write address counter counts a write clock WCK and determines output as a write address, while read address counter counts a read clock RCK and determines output as a read address. The position of LSB in both the counters is shifted by the same number of bits at predetermined intervals, and the position of LSB of the read address counter before shifting is corresponded with the shifted position of the write address counter after shifting. Both the counters count and determine their outputs as write and read addresses. Thus, memory capacity can be reduced, and data can be written and read with different write and read orders.
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