| 摘要 |
The invention relates to a tester head which interfaces with high speed protocol memories such as RAMBUS devices. A head in a memory test system conditions the signals applied to the Device Under Test (DUT). A memory of this type further comprises a base providing all the algorithmic funcionality. A high speed protocol memory test head according to the invention comprises a test generator connector for receivong the test signals form the test generator, a control packet generator for generating row and column control packets basing on control signals (including address) from the test generator connector, a data packet generator for generating data packets from data streams from the test generator connector, the inputs of the control packet generator and the data packet generator being connected to the test generator connector, serialisers respectively connected to the outputs of the control packet generator for transforming wide and slow packets into high-speed and narrow packets, pin electronics for interfacing to a high speed protocol memory DUT, deserialiers for transforming high-speed and narrow DUT-output packets back to wide and slow packets, a data comparator for comparing the deserialised DUT-output data with the refence data from the data packet generator and a fault logger connector for feeding the comparison results from the data comparator to the fault logger. |
