| 摘要 |
Readout circuitry (10) for a magnetic tunneling junction (MTJ) memory cell, or an array of MTJ memory cells, is disclosed which requires a varying reference voltage equal to (Vbias1/2)(1 + Rmin/Rmax), where Vbias1 is a clamping voltage applied to the readout circuitry, Rmin is a minimum resistance of the magnetic tunneling junction memory cell (27), and Rmax is a maximum resistance of the magnetic tunneling junction memory cell (17). A reference voltage generator is disclosed which generates the reference voltage (43) and includes an operational amplifier (45) and two MTJ memory cells connected to provide an output signal equal to (Vbias1/2)(1 + Rmin/Rmax). |
