发明名称 |
Embedded memory architecture for video applications |
摘要 |
A memory has a wide data bus to an associative array processor. An entire row of the memory is read to or written by the associative array processor in a single access cycle. A data I/O controller is also coupled to the wide data bus between the memory and associative array processor. The data I/O controller has multiplexers that select one word from the wide data bus for access by a word-width system bus. A block-access mode selects a multi-word block in a row for access. A register latches in a block or row from the wide data bus, and words from the register are then accessed by the data I/O controller. The wide data bus is at least 1024 bits wide, and can be 5760 bits wide, enough for the associative array processor to read an entire line of a graphics or video picture.
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申请公布号 |
US2002105522(A1) |
申请公布日期 |
2002.08.08 |
申请号 |
US20000681053 |
申请日期 |
2000.12.12 |
申请人 |
KOLLURU MAHADEV S.;ONG ADRIAN E. |
发明人 |
KOLLURU MAHADEV S.;ONG ADRIAN E. |
分类号 |
G09G5/39;(IPC1-7):G06F13/14 |
主分类号 |
G09G5/39 |
代理机构 |
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地址 |
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