| 摘要 |
A memory device is described which has an n-channel field effect transistor coupled between a memory cell and a data communication line. An NPN bipolar junction transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar junction transistor is described as coupled to a body of the n-channel access transistor. During operation the n-channel field effect transistor is used for writing data to a memory cell, while the NPN bipolar junction transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.
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