Digital fractional phase detector

摘要

A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.