发明名称 |
MULTIPLEX SEPARATION PROCESSOR |
摘要 |
PROBLEM TO BE SOLVED: To provide a multiplex separation processor which can reduce power consumption due to wasteful operations during waiting of a TS packet input and the processing of the TS packet. SOLUTION: System clock control pats 21 to 24 for controlling the supply of a system clock to a function block by a microcode instruction are arranged in respective function blocks of a descrambler 201, a filter 202, an output interface 203 and a TS packet 209. The function blocks become operative when the system clock is supplied, and become inoperative, when the supply of the system block is stopped. |
申请公布号 |
JP2002217853(A) |
申请公布日期 |
2002.08.02 |
申请号 |
JP20010008462 |
申请日期 |
2001.01.17 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
ARAKAWA HIROSHI;TANAKA KAZUHISA |
分类号 |
G06F1/04;H04H20/00;H04H40/18;H04J3/00;H04L7/08;H04N5/44;H04N7/167;H04N19/00;H04N19/102;H04N19/134;H04N19/177;H04N19/423;H04N19/44;H04N19/70;H04N21/438;H04N21/4385;H04N21/442 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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