MULTIPLE INPUT PHASE LOCKED LOOP WITH HITLESS REFERENCE SWITCHING

摘要

PROBLEM TO BE SOLVED: To provide a phase locked loop(PLL) with a reference switching mechanism that alleviates problems such as phase deviation with prior art. SOLUTION: A clock recovery circuit for recovering clock signals from one of a plurality of input reference signals, includes an acquisition phase locked loop(PLL) for each input. The acquisition PLL has a phase comparator for comparing the phase of an input signal to a feedback signal, and first and second digital controlled oscillators(DCOs) receiving an input from the phase comparator. An output PLL has a phase comparator selectively connectable to the output of each of the acquisition PLLs. The output PLL has a first DCO providing an output for the circuit and a second DCO in a feedback loop providing a feedback signal to the phase comparator of the output PLL. The second DCO of the output PLL has a control input to introduce a phase offset therein relative to the first DCO of the output PLL.