发明名称 MULTI-INPUT ADDITION AND SUBTRACTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To perform addition and subtraction of operands of three or more inputs, as accurately as possible. SOLUTION: This multi-input adding and subtracting circuit comprises a maximum index part detecting means 100 for detecting the maximum index part by comparing with each other, the index parts of operands of n (n>=3) in quantity, a plurality of sub tractors 107 and 108 for obtaining the difference between the maximum index part detected by the detection means 1 and the index parts of the other operands, a selection means 101 for selecting a mantissa part corresponding to the maximum index part detected by the detection means 1, shifting means 109 and 110 for performing a digit adjustment shifting of the mantissa part of the operand which is not selected by the selection means by the amount of difference of the corresponding index part, and a bit expansion means 121. From the results of shift out from the shifting means, a guard bit G, a bit R, and a sticky bit St are obtained, and the bit expansion means adds a bit for stopping propagation of carrying by the addition of sticking bits St, between the sticky bit St and a round bit R by the number of digits of (log2n) bit or larger.
申请公布号 JP2002215384(A) 申请公布日期 2002.08.02
申请号 JP20010007724 申请日期 2001.01.16
申请人 TOSHIBA CORP 发明人 IDE YUKIHIRO
分类号 G06F7/38;G06F7/485;G06F7/50 主分类号 G06F7/38
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