| 摘要 |
PROBLEM TO BE SOLVED: To eliminate the need for correcting the arrangement of a buffer and power-supply GND wiring after a cell is arranged by satisfying skew in a CTS design, and at the same time by minimizing a voltage drop. SOLUTION: Virtual lattices 11 and 12 are set to a layout region, a plurality of rows j, j+1,..., j+x, j, j-1,..., and j-y is arranged in a partial region 13 divided by the lattices 11 and 12. The cell is arranged so that timing restriction is satisfied for each row (steps S1 to S5). Then, in a CTS design step S6, the current consumption of each row is investigated, and a clock buffer B1 is arranged in the row having a small amount of current consumption based on current consumption information.
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