| 摘要 |
PROBLEM TO BE SOLVED: To reduce the area of a full CMOS cell. SOLUTION: A memory cell for an SRAM has a full CMOS cell structure in which three different conductivity type wells are arranged successively. Further, the cell has a first and second contact holes extended on the impurity region of a fixed MOS transistor form the upper sections of the first and second gates 3 and 4, and formed in a self-alignment manner to the first and second gates 3 and 4, and the first and second local wirings 7 and 8 formed in the contact holes. |
