Buffers with reduced voltage input/output signals

摘要

A buffer circuit that operates with reduced voltage input and output signals receives an input signal having reduced voltage range and generates an output signal with the reduced voltage range. The reduced voltage range is from 0 volts to VRED, where VRED is less than VCC, the voltage used to operate most of the logic in the integrated circuit. The use of a buffer circuit that receives and generates signals with a reduced voltage range advantageously reduces power consumption.