| 摘要 |
The invention relates to a switching device for switching input data frames (IDF) from a plurality of N input lines (i1, i2, . . . in, iN) to output data frames (ODF) on a plurality of M output lines (o1, o2, . . . on, oM). The switching device contains a number K of switch pattern units, each containing a specific switch pattern. A number K of frame store memories (FSMj) each store all input data frames from all input lines in every frame period. Each frame store memory is used for selecting bits to a sub-group of M/K output lines. The parallelly working units (u1, u2, . . . uK) each sequentially select a plurality of M/K bits from the stored input data frames and simultaneously assign the selected bits to the output data frames on the respective sub-group of output lines. The selection and assigning of bits in each unit is performed at a M/K times higher clock rate than the bit rate on the input data lines. Thus, a bit-orientated reading of input data frames and writing of output data frames is achieved which allows a flexible switching of full rate as well as sub-rate input PCM data frames.
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