| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a CID pattern generator that can optionally set a byte length of a consecutive pattern and realize a high-speed output bit rate. SOLUTION: A pseudo random signal generating section 24 consists of a logical arithmetic circuit 25, a 1st latch shift circuit 26, a 2nd latch shift circuit 29, a synthesis circuit 32 and a control circuit 35. In the case that a length M of a '0s' or '1s' consecutive pattern inserted to a frame is not an integer multiple of an output byte width N, data in the 1st and 2nd latch shift circuits 26 and 29 are shifted to lower digits by excess bytes by utilizing a time while SOH data are outputted, and a synthesis circuit 32 inserts the excess consecutive pattern to a pseudo random signal at a head outputted in a succeeding frame and outputs the resulting frame.</p> |
