发明名称 LOGIC SIMULATION METHOD, AND RECORDING MEDIUM RECORDING PROGRAM FOR LOGIC SIMULATION
摘要 PROBLEM TO BE SOLVED: To improve accuracy of a floating error result list to a wiring driven by a three state buffer. SOLUTION: In steps 6 and 8, a time when a logical sum signal of all enable input changes from a logical value 1 to a logical value 0 or X is stored as a floating starting time. In steps 7, 9, 10, and 11, when the logical sum signal of all the enable input changes to the logical value 1, a floating period is calculated from the floating starting time. When it is greater than a previously set check value, a floating error of the wiring is registered.
申请公布号 JP2002207782(A) 申请公布日期 2002.07.26
申请号 JP20010003279 申请日期 2001.01.11
申请人 NEC MICROSYSTEMS LTD 发明人 NOSEYAMA HAJIME
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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