发明名称 |
Semiconductor device manufacturing method using metal silicide reaction after ion implantation in silicon wiring |
摘要 |
A wiring of silicon is formed on a surface of a semiconductor substrate. Part of the wiring is covered with a resist pattern. Ion implantation is conducted on the substrate using the resist pattern as a mask and then the resist pattern is removed. An upper section of the wiring with a thickness of at least 5 nm is removed to minimize thickness of the wiring. Reaction is caused between a surface section of the wiring of which thickness is thus reduced and a metal which reacts with silicon to form suicide to thereby form a metal silicide film on a surface of the wiring. Resistance of the wiring can be reduced with good reproducibility.
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申请公布号 |
US2002098683(A1) |
申请公布日期 |
2002.07.25 |
申请号 |
US20010995575 |
申请日期 |
2001.11.29 |
申请人 |
FUJITSU LIMITED |
发明人 |
YASUMOTO TAMIHIDE |
分类号 |
H01L21/265;H01L21/266;H01L21/28;H01L21/3205;H01L21/321;H01L21/336;H01L21/8238;H01L23/52;H01L27/092;H01L29/78;(IPC1-7):H01L21/44;H01L21/476 |
主分类号 |
H01L21/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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