| 摘要 |
A device architecture and process for fabricating a semiconductor device incorporating a p-n junction. Generally, an integrated electronic device includes a substrate layer of semiconductor material having a major surface formed along a crystal plane. In a preferred embodiment, a first region of a first conductivity type is formed in the substrate layer and a substantially monocrystalline semiconductor layer is deposited on the first region. Within this layer there is a first portion of a second conductivity type and a second portion of the first conductivity type formed over the first portion. The first portion and the first surface region form a pn junction. In an exemplary construction of the invention the deposited layer includes a bipolar transistor collector of a first conductivity type and a bipolar transistor base of a second conductivity type formed over the collector and a portion extending from the major surface to the collector. A conductive layer extending between the major surface and the emitter provides electrical connection to the collector. According to an associated method of fabricating a semiconductor device a substrate layer includes an upper-most surface formed along a first plane and a first doped region of a first conductivity type is formed above the first plane. A second doped region of a second conductivity type is formed over the first doped region resulting in formation of a p-n junction in a second plane above the first plane. An electrical connection is provided to the first doped region with a conductor formed between the first and second planes.
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