发明名称 |
Synchronous semiconductor device for adjusting phase offset in a delay locked loop |
摘要 |
A synchronous semiconductor device having a delay locked loop capable of adjusting phase offset between an external clock signal and an internal clock signal after a packaging process is completed is disclosed. The disclosed synchronous semiconductor device may include a replica delay for replicating delay time of an internal circuit and a delay controller for controlling the replicated delay time.
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申请公布号 |
US2002097074(A1) |
申请公布日期 |
2002.07.25 |
申请号 |
US20010033004 |
申请日期 |
2001.12.28 |
申请人 |
KIM SE-JUN;WEE JAE-KYUNG;PARK YONG-JAE |
发明人 |
KIM SE-JUN;WEE JAE-KYUNG;PARK YONG-JAE |
分类号 |
G11C11/407;G06F1/10;G11C7/10;G11C8/00;G11C29/50;H03K5/13;H03L7/081;H03L7/089;(IPC1-7):H03L7/06 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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