发明名称 Input/output buffer capable of supporting a multiple of transmission logic buses
摘要 An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor-type signal to determine the type of microprocessors used. According to the microprocessor type, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various types of microprocessors.
申请公布号 US6420898(B2) 申请公布日期 2002.07.16
申请号 US20000733697 申请日期 2000.12.08
申请人 VIA TECHNOLOGIES, INC. 发明人 HUANG JINCHENG;CHANG NAI-SHUNG;LIAW YUANGTSANG
分类号 H03K19/0185;(IPC1-7):H03K17/16;H03K19/003 主分类号 H03K19/0185
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