| 摘要 |
A semiconductor device comprises a plurality of superposed layers including a predetermined layer provided, in a peripheral part of a chip, with a dummy pattern of a material that is the same as that forming a wiring pattern formed in the same predetermined layer, the dummy pattern being formed on an inner side of a dicing region. The ratio of an area of the dummy pattern in a planar region defined by the inner edge of the dummy pattern, the outer edge of the dicing region and two optional, parallel lines to that of the planar region is 50% or above.
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