| 摘要 |
PURPOSE: A device for controlling a reset composition of a CPU is provided to minimize the number of buffers for setting initial values in accordance with a hardware reset in a CPU of the MPC(Multimedia Personal Computer) 8xx system of the Motorola company. CONSTITUTION: A plurality of external integrated circuits(20-40) is provided for performing a given inherent function. A data bus(D-BUS) transmits data between a CPU(10) of the MPC 8xx system and each integrated circuit(20-40). An address bus(A-BUS) transmits an address from the CPU(10) to each integrated circuit(20-40). A buffer(BUF1) is controlled in an internal signal being generated in the CPU(10) according to a reset of a hardware and applies or cuts-off a power voltage(VCC) to a bit of the data bus(D-BUS) to be set as a setting value '1' for using the integrated circuits(20-40) initially through a pull-up resistor(R1). A NOR gate(NOR1) NORs an internal signal being generated in the CPU(10) in accordance with a reset of the hardware in the CPU(10). A buffer(BUF2) is continuity-controlled in the CPU(10) according to an output of the NOR gate(NOR1), connects a bit of the data bus(D-BUS) to a ground through a pull-up resistor(R2) at a normal operation and cuts-off the bit in the case that a hardware reset is generated. A multiplexer(MUX1) receives an internal signal being generated in the CPU(10) at each selection terminal according to a hardware reset in the CPU(10), selects a signal being applied from the bit of the data bus(D-BUS), and applies the signal to a main control unit(11) in the CPU(10) as a reset composition signal(CONF-WORD).
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