A SYMMETRIC ARCHITECTURE FOR MEMORY CELLS HAVING WIDELY SPREAD METAL BIT LINES

摘要

PROBLEM TO BE SOLVED: To provide a symmetric architecture for memory cells by segmenting bit lines into small blocks for reducing the total time of programming voltages interfering cells. SOLUTION: A memory array includes a first plurality of metal bit lines, a second plurality of diffusion bit lines and a third plurality of select transistors. There are more than two diffusion bit lines per metal bit line.