发明名称 METHOD OF VERIFYING DESIGNED CIRCUIT
摘要 PURPOSE: To provide a method of verifying a designed circuit capable of easily verifying an LSI and a wiring board circuit in a designing stage of the circuit. CONSTITUTION: The electric characteristic of the designed circuit in the designing stage is detected and compared with the reference data by analyzing the simulated circuit on a computer image plane, to specify items, places and the like to be corrected, and the contents of correction is displayed on the specified place of the designed circuit to correct the design of the circuit. Thus the efficiency in designing the circuit can be improved.
申请公布号 KR20020052939(A) 申请公布日期 2002.07.04
申请号 KR20010080477 申请日期 2001.12.18
申请人 SONY CORPORATION 发明人 MURAYAMA TOSHIO
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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