IMPROVED ARCHITECTURE AND INTERCONNECT FOR PROGRAMMABLE LOGIC CIRCUITS

摘要

An improved programmable logic device and interconnect architecture is provided. In one embodiment an interconnect network provides programmable routing between calls. In one embodiment the interconnect network includes first routing lines (314) of a first level of routing lines, second routing lines (324) of a second level of routing lines and third routing lines (330, 332, 334, 336, 338) of a third level of routing lines. The first and second routing lines are programmably and bidirectionally coupled to the third routing lines such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from the third routing lines to the first routing lines and second routing lines.