| 摘要 |
An accurate target detection system. The system includes a sensor (22) that receives electromagnetic signals and provides electrical signals in response thereto. A non-uniformity correction circuit (28, 38, 52) corrects non-uniformities in the sensor (22) based on the electrical signals and provides calibrated electrical signals in response thereto. A third circuit (30, 32, 34, 38, 42, 44, 52) determines if a target signal is present within the calibrated electrical signals and provides a target detection signal in response thereto. A fourth circuit (38, 40, 48) selectively activates or deactivates the non-uniformity correction circuit (28, 38, 52) based on the target detection signal. In a specific embodiment, the sensor (22) is an array of electromagnetic energy detectors (22), each detector providing an electrical detector output signal The non-uniformity correction circuit (28, 38, and 52) includes circuit for compensating for gain, background, and noise non-uniformities (28, 38, and 52) in the electromagnetic energy detectors. The non-uniformity correction circuit (28, 38, and 52) includes a detector gain term memory (28) for storing detector gain compensation values. The detector gain compensation values are normalized by noise estimates unique to each of the detectors. The third circuit (30, 32, 34, 38, 42, 44, and 52) includes a signal enhancement circuit for reducing noise (34, 42) in the calibrated electrical signals. The third circuit (30, 32, 34, 38, 42, 44, and 52) includes a noise estimation circuit (32, 38) that estimates noise in each of the detector output signals and provides noise estimates in response thereto. The noise estimation circuit (32, 38) further includes a noise estimator circuit (38) and a recursive background estimator (32). The third circuit (30, 32, 34, 38, 42, 44, 52) further includes a subtractor (30) for subtracting background from the calibrated electrical signals and providing background subtracted signals in response thereto. The signal enhancement circuit (34, 42) includes a frame integrator circuit for adding frames of image data (34), each frame containing data corresponding to the background subtracted signals and providing summed frames in response thereto. The third circuit (30, 32, 34, 38, 42, 44, 52) includes a first threshold circuit (44) for comparing the filtered signal to a first threshold and a second threshold and providing a threshold exceedance signal if the filtered signal is between the first threshold and the second threshold. |
