发明名称 |
DUTY CYCLE CONTROL LOOP |
摘要 |
An output circuit generates an output signal. The output signal has a duty cycle from an input signal. A level extractor couple to the output circuit to extract a direct current (DC) level from the output signal. The DC level is a representative of the duty cycle. An integrator couple to the level extractor to integrate the DC level. The integrator generates a current control signal to adjust the duty cycle.
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申请公布号 |
US2002084817(A1) |
申请公布日期 |
2002.07.04 |
申请号 |
US20000752250 |
申请日期 |
2000.12.28 |
申请人 |
NAIR RAJENDRAN;WRIGHT CHANTAL;MOONEY STEPHEN;NARENDRA SIVA G. |
发明人 |
NAIR RAJENDRAN;WRIGHT CHANTAL;MOONEY STEPHEN;NARENDRA SIVA G. |
分类号 |
H03K5/156;(IPC1-7):H03K3/017;H03K5/04;H03K7/08 |
主分类号 |
H03K5/156 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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