SYSTEM CLOCK SYNCHRONISATION USING PHASE-LOCKED LOOP

摘要

An apparatus for synchronizing the system clocks of wireless devices in a digital communications system is presented. A digital phase-locked loop is employed. The phase-locked loop may include a counter which is incremented by a local devi ce system clock and latched by a frame synchronization marker received from a remote device, whereby the counter output comprises a feed forward signal. The phase-locked loop may alternatively include a counter that reflects the level of data stored i n receive and/or transmit FIFO buffers. The loop output signal controls the frequency of the system clock oscillator.