| 摘要 |
A P-channel transistor is disclosed having P+ source and drain regions formed in a N- well, which is formed in a P- substrate. A third P+ region is provided that functions as a well tie. When the P-channel transistor is used as the pull-up transistor in a CMOS "push-pull" output buffer circuit, the P+ well tie prevents undesired current flow from the bus back to the positive voltage supply. This prevents potential damage to the power supply plane and any additional components connected thereto. In another aspect, the N- well has formed therein both a P+ and N+ well tie. Additional switch circuitry is provided which allows for upper level programmability or selection of either one or both of the two well ties, depending upon the ultimate circuit configuration.
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