| 摘要 |
PROBLEM TO BE SOLVED: To avoid delay of an operation clock by avoiding a state that an instruction which is not used at present is fetched to waste processing time while a branching instruction is executed. SOLUTION: Memory data access structure and its method are suitable for use in a processor. To the respective instructions to be executed by the processor, an execution result is recognized by the processor and transferred to a cache memory through a control signal. When no instruction to be fetched is stored in the cache memory, the cache memory decides whether or not the instruction should be fetched from an external memory according to the control signal. Many operation clock cycles wasted in the processor of the conventional technology are saved by compensating the state which is missed to be fetched by the cache memory, namely, a mistake by the cache memory irrespective of whether or not the processor is provided with branching prediction mechanism. Efficiency and performance of the processor are efficiently enhanced.
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