| 摘要 |
<p>A bias circuit (101) that provides biasing for a differential circuit (103). The bias circuit (101) includes first and second transistors (Q3, Q4), first and second impedance devices (R1, R2), a reference current source (201) and an amplifier (203). The first and second transistors (Q3, Q4) each have a control input and a current path coupled between a first node (V1) and ground, where the control inputs of the first and second transistors receive the differential signal (VIN). The impedance devices (R1, R2) are each coupled between a control input of one of the first and second transistors and a second node (V2). The reference current source (201) provides a reference current (IREF) for the first node (V1) and the amplifier (203) has an input coupled to the first node (V1) and an output coupled to the second node (V2). The transistors (Q3, Q4), (Q1, Q2) of the bias circuit and the differential circuit, respectively, may be matched, NPN bipolar junction transistors with emitters connected to ground. A filter capacitor (C1) may be coupled between the first node (V1) and ground and operates as a low pass filter.</p> |
