发明名称 PLL circuit
摘要 A phase lock signal generation unit includes a phase difference signal generation unit for generating a phase difference signal between a reference clock signal and an internal clock signal; a phase shift detection unit for generating a signal indicating a release of a phase lock signal LOCK when phase shifts occur continuously two times in predetermined intervals in a phase different signal; and a wait time count unit which is controlled by an output from the phase shift detection unit, and releases the phase lock signal.
申请公布号 US6411141(B1) 申请公布日期 2002.06.25
申请号 US19990285073 申请日期 1999.04.02
申请人 NEC CORPORATION 发明人 KANNO HIROSHI
分类号 H03L7/087;H03L7/095;H03L7/18;(IPC1-7):H03L7/095;H03L7/06 主分类号 H03L7/087
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