Single ended data bus equilibration scheme

摘要

A method and apparatus for biasing an open ended bus line to a predetermined voltage just prior to the arrival of a data signal. The bias on the bus line is used to move the voltage of a received data signal closer to trip points used to determine the logical value of the data signals. The equilibration circuit may be are enabled by a clock signal derived from a sense amplifier clock signal to ensure that the bias voltage is applied to the bus line just prior to the arrival of the data signal.