| 摘要 |
PURPOSE: A metal electrode lines formation method of semiconductor devices is provided to reduce a misalignment by simultaneously forming a via hole and a trench using a self-aligned etching process. CONSTITUTION: A first to a fourth insulators are sequentially formed on a first metal wire, wherein the first and third insulators have different etching selectivity compared to the second and fourth insulators. After forming a barrier pattern on the resultant structure, the third and fourth insulators are selectively etched by using a via hole mask pattern having a wider width compared to the barrier pattern. The fourth insulator is two-step etched by using the barrier pattern and the third insulator as a mask. A via hole(28) and a trench(27) are simultaneously formed by sequentially etching the third and second insulators using the fourth insulator pattern as a mask. A second metal wire(30) is formed by filling the trench(27) and the via hole(28).
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