| 摘要 |
PROBLEM TO BE SOLVED: To eliminate the problem of a product designed, based on the sub- halfmicron rule or less than 0.5μm, showing a noticeable specificity of pattern, and wide adjacent interconnections and dot interconnection patterns formed independently from each other are disposed at important positions of the product, and these patterns easily change in size due to the specificity of their pattern structures, and changes in size and shape cause decline in yields and reliability of the product. SOLUTION: For example, power supplying interconnections 20 and dot interconnections 40 formed independently from each other, which are used inside a chip and have a large influence on yields, are selected and are formed at intervals according to the minimum design rule, Around a chip having the worst exposed state, check patterns are disposed to monitor the shapes of the interconnection patterns immediately after they are formed. Thereby, the yields of the product can be increased by screening out defective wafers, and further the exposure conditions can be optimized. |
