发明名称 Method, integrated circuit and test system for adjusting internal timing or associated reference quantity in integrated circuits, for use in particular in read-only memory circuits
摘要 The method for adjusting the duration of internal timing to a value close to the typical value (T0) of that duration includes the inducement of internal timing (TEMP) in an integrated circuit, and the sending of calibration values (K1,K2,...K40) in sequence from a tester to the input of the integrated circuit. The expiration of internal timing determines the calibration datum (K) as the last received calibration value or that in the train of received values, which is applied to an adjustment device (AJUST) for adjusting the duration of internal timing in the integrated circuit (CI). The integrated circuit comprises an internal timing generator circuit (GEN-TEMP) operated on the basis of a reference quantity such as current or capacitance (IREF, CREF), a register (REG) for temporary storage of calibration values input as data from the tester, a control circuit (CL) receiving the test instructions, and a memory element M(KE) for storing the calibration datum. Each calibration value corresponds to a ratio of the typical value (T0) to the total time lapsed from the start of internal timing to the instant when the value is sent. The device for adjustment is initialized to a calibration value, and each calibration value sent is affected by the initialization value. The first calibration value is sent after a lapse of a minimum duration of internal timing. The adjusted reference circuit is a current source, a network of capacitors, or a network of resistors. The method is applied to a read-only memory integrated circuit for adjusting the duration of programming signal. The method includes the launch of programming of any data at an address in the integrated circuit, and sending of calibration values as data to the input of integrated circuit. The method includes the programming of the calibration datum after sending all calibration values defined for the internal timing a function of specifications of the integrated circuit. The system for testing in parallel of integrated circuits of the same technology comprises a table (TAB) of calibration values for adjusting the internal timing.
申请公布号 FR2818424(A1) 申请公布日期 2002.06.21
申请号 FR20000016703 申请日期 2000.12.20
申请人 STMICROELECTRONICS SA 发明人 TAILLIET FRANCOIS
分类号 G11C7/10;G11C7/20;G11C7/22;G11C16/32;G11C29/02;G11C29/14;G11C29/50;(IPC1-7):G11C7/22;G01R31/00;G01R31/303 主分类号 G11C7/10
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