PLL FOR SYNTHESIZING FREQUENCIES HAVING RATIONAL RELATIONSHIPS WITH A REFERENCE FREQUENCY

摘要

A single loop PLL frequency synthesizer, operates at comparison frequencies above 100 MHz, with excellent phase noise performance, but allows for small frequency steps lower than 10 kHz and is suitable for integration within ASICs. The output frequency and the reference clock frequency always have a rational relationship (i.e. the ratio of the two frequencies can always be represented as a ratio of two integer numbers). This ratio can always be expanded into various expressions of equivalent fraction expansions. The equivalent fractions take the form of a series of divided, added or subtracted terms, each term itself being a rational number. For each synthesized frequency, the computation of expansion terms yields specific, different values of the terms, with possibly multiple solutions. The realization in hardware of the computed fraction expansion terms is achieved by the means of a specific combination of frequency division and frequency translation of the reference clock frequency and/or of the oscillator frequency.