发明名称 |
Scheduler for a data memory access having multiple channels |
摘要 |
A scheduler configured to schedule multiple channels of a Data Memory Access (DMA) includes a shift structure having entries corresponding to the multiple channels to be scheduled. Each entry in the shift structure includes multiple fields. Each entry also includes a weight that is determined based on these multiple fields. The scheduler also includes a comparison-logic circuit that is configured to then sort the entries based on their respective weights.
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申请公布号 |
US2002078267(A1) |
申请公布日期 |
2002.06.20 |
申请号 |
US20000740669 |
申请日期 |
2000.12.18 |
申请人 |
ROZARIO RANJIT J.;CHERUKURI RAVIKRISHNA |
发明人 |
ROZARIO RANJIT J.;CHERUKURI RAVIKRISHNA |
分类号 |
G06F12/06;G06F3/06;G06F12/00;G06F13/28;G06F13/42;(IPC1-7):G06F13/28;G06F3/02;G06F3/05;G06F5/00 |
主分类号 |
G06F12/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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