| 摘要 |
According to the present invention, a first plurality of solder bumps are arranged the active surface of an integrated circuit die in the form of a grid comprising a plurality of rows and a plurality of columns, where the plurality of rows are parallel to two opposing edges of the active surface and the plurality of columns are perpendicular to the plurality of rows. The plurality of columns are separated by a distance D. Each of the solder bumps in every other row is separated from an adjacent solder bump in that row by a distance 2D such that the each of these solder bumps is disposed along a first group of the plurality of columns. Each of the solder bumps in the remaining rows, is separated from an adjacent solder bump in that row by the distance 2D such that the solder bumps in the remaining rows are disposed along a second group of the plurality of columns. Each column within the second group of columns is adjacent to, and in between, two of the columns within the first group of columns. In other words, the solder bump pads are staggered.
|
