| 摘要 |
A bias circuit is described for use in biasing an operational amplifier to maintain a constant transconductance divided by load capacitance (i.e. a constant gm/CL) despite temperature and process variations and despite body effects. In one example, the bias circuit includes a pair of current source devices and a switched capacitor (SC) equivalent resistor circuit for developing an equivalent resistance between the current source devices. The equivalent resistor circuit includes a sampling capacitor. First and second clock inputs are connected to the capacitor providing non-overlapping clock signals at a predetermined sampling frequency to establish a resistance equivalent. By providing an SC equivalent resistor circuit clocked by non-overlapping fixed clock signals, the gm/CL of the bias circuit is maintained substantially constant. Hence, a fixed bandwidth is maintained within the operational amplifier being biased. When employed in connection with operational amplifiers of an SC circuit, the constant bandwidth enables the SC circuit to operate at a constant switching speed despite temp and process variations. Furthermore, by positioning the resistance equivalent circuit between the current source devices of the bias circuit, voltage differentials between the sources are eliminated thereby removing any threshold voltage mismatch and thus compensating for body effect variations. Other bias circuit examples are also described including a stray insensitive bias circuit and a bias circuit employing three mutually non-overlapping clock signals.
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