Integrated circuit cache memory, with DRAM cells, of content addressed memory type (CAM), uses temporary storage flip-flops and single comparator to compare contents of flip-flop with state function of read points

摘要

For each matrix column a second temporary storage flip-flop (34) for complementary signals is read by the amplifier (SAi). The respective functions of the two flip-flops (33,34) are interchangeable. For each matrix column, a unique mask register (37) is designed to inhibit the comparison of the correspondence column . Integrated circuit cache memory which includes a matrix array (10) of memory elements (20) associated, in columns, with two lines of complementary bits (BLi,BLi). Each memory element includes, in series between a first bit line (BLi) and a reference potential, a transistor (T) and capacitor (C). the transistor grid is connected to a word line (WLj); and for each matrix network column; a read amplifier (S Ai) between the bit lines and two complementary read points; a first temporary storage flip-flop (33) for a value to compare with one of the column memory elements, and; a unique element (31) for comparing the contents of the first flip-flop with a state function for one of the read points.