Semiconductor memory device and data processing system having semiconductor memory device

摘要

A semiconductor memory device having a DDR mode includes a first comparison logic circuit comparing the lower bits of a specified memory address for reading operation with the lower bits of a specified memory address for the preceding writing operation, a second comparison logic circuit detecting if the other bits than the lower bits of the specified memory address for reading operation respectively match the other bits than the lower bits of the specified memory address for the preceding writing operation, and a third comparison logic circuit detecting that, when matching can be obtained in the comparison result from the second comparison logic circuit, the lower bits of the specified memory address or secondary memory address for the reading operation match the lower bits of the specified memory address or secondary memory address for the preceding writing operation, on the comparison result from the first comparison logic circuit.