发明名称 |
Built-in self-test arrangement for integrated circuit memory devices |
摘要 |
An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit. |
申请公布号 |
US2002071325(A1) |
申请公布日期 |
2002.06.13 |
申请号 |
US20010941075 |
申请日期 |
2001.08.28 |
申请人 |
HII KUONG HUA;CLINE DANNY R.;POWELL THEO J. |
发明人 |
HII KUONG HUA;CLINE DANNY R.;POWELL THEO J. |
分类号 |
G01R31/30;G06F1/08;G06F11/27;G11C5/14;G11C29/14;G11C29/16;G11C29/36;G11C29/38;G11C29/50;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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