Controlled anneal conductors for integrated circuit interconnects

摘要

A method is provided for manufacturing an integrated circuit on a semiconductor wafer having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier layer is deposited to line the opening. A seed layer is deposited on the barrier layer and securely bonds to the barrier layer. A conductor layer is deposited to fill the channel opening over the barrier layer. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel. The semiconductor wafer is then subjected to a two step timed anneal.