A bootstrapped shift register in which each stage comprises only four transistors of the same type, and a bootstrap capacitor. Each stage of the register is clocked by a pair of clock signals, one of which effectively provides a clocked supply rail voltage, sothat no separate DC supply is required.
申请公布号
WO0245091(A1)
申请公布日期
2002.06.06
申请号
WO2001GB05183
申请日期
2001.11.23
申请人
IMPERIAL COLLEGE OF SCIENCE, TECHNOLOGY AND;LEE, MICHAEL, JOHN;BURDETT, ALISON;CHEN, YUNG, CHIN
