发明名称 |
Method of making floating gate non-volatile memory cell with low erasing voltage |
摘要 |
A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.
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申请公布号 |
US6399444(B1) |
申请公布日期 |
2002.06.04 |
申请号 |
US20000521876 |
申请日期 |
2000.03.08 |
申请人 |
SGS-THOMSON MICROELECTRONICS S.R.L. |
发明人 |
CAPPELLETTI PAOLO |
分类号 |
H01L21/8247;H01L21/28;H01L27/115;H01L29/423;H01L29/49;H01L29/51;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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