发明名称 |
FUNCTION BLOCK ARCHITECTURE FOR GATE ARRAY |
摘要 |
A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.
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申请公布号 |
WO0125976(A3) |
申请公布日期 |
2002.05.30 |
申请号 |
WO2000US27655 |
申请日期 |
2000.10.06 |
申请人 |
LIGHTSPEED SEMICONDUCTOR CORPORATION |
发明人 |
HOW, DANA;SRINIVASAN, ADI;EL GAMAL, ABBAS |
分类号 |
G06F1/10;G06F17/50;(IPC1-7):G06F17/50;H03K19/173;H03K19/177 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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